1. Field of the Invention
The present invention relates to integrated circuits having improved protection from electrostatic discharge.
2. Description of the Prior Art
The protection of integrated circuits (ICs) from electrostatic discharge (ESD) events is a significant part of integrated circuit design. A typical protection circuit may include diodes and/or transistors that arc connected between the input or output bondpads and a power supply conductor (V.sub.SS or V.sub.DD). A ESD voltage on the bondpad (e.g., greater than 100 volts) is then conducted safely away from the operational circuitry (typically an input buffer or output buffer) that is connected to the bondpad. For example, referring to FIG. 3, protection diode 32 conducts when the voltage on bondpad 31 exceeds a diode threshold voltage drop (about 0.6 volts) above the voltage on the power supply conductor 35, which in operation is connected to the positive power supply voltage (V.sub.DD). Similarly, protection diode 33 conducts when the voltage on the bondpad falls sufficiently below the voltage on the power supply conductor 36, which in operation is connected to the negative power supply voltage (V.sub.SS). Most ESD problems occur during shipping and handling, when the power supply voltages are not applied to the IC chip. However, the capacitive coupling between the power supply conductors and the semiconductor substrate serves to provide a sink for the excess voltages. In this manner, the voltage conducted from the bondpad 31 to the input or output buffer circuitry 34 does not exceed an acceptable level. Various forms of protection devices arc described in U.S. Pat. No. 4,821,089, coassigned with the present invention.
However, when diodes are used as the protective device, a problem arises when the bondpad is connected to a signal bus that may operate at a higher voltage than the protected integrated circuit. For example, in some cases it is desirable to power-down a given integrated circuit while the bus to which it is connected remains active. In that case, a high logic level (e.g., +5 volts) may be present on one or more of the bondpads, while the V.sub.DD power supply conductor to the powered-down IC is at 0 volts. Therefore, a protective device (e.g., diode 32) could be forward biased, causing a potential electrical overstressing situation, and loading down the bus. In another situation, it is sometimes desirable to use various powering schemes for the integrated circuits on a board (e.g., 5 volts and 3 volts, etc.). If an integrated circuit that operates at the lower level is connected to the bus, then a high-level logic signal could also cause a protective device (diode 32) to conduct, undesirably loading down the bus and overstressing the lower-voltage integrated circuit, Alternatively, transistors may be used as protective devices to provide a higher voltage threshold before conduction occurs, thereby preventing such undesired conduction. However, in some situations, transistors have not provided a sufficiently high degree of protection, due to their higher resistance. In particular, the protection of output buffers from ESD damage has been a problem for workers in the art. Therefore, it is desirable to have an improved technique for protecting integrated circuits from electrostatic discharge that avoids certain problems created by prior art techniques.